1. Field of the Invention
The present invention relates to displaying images, especially to system for displaying images by utilizing a vertical shift register circuit for generating non-overlapped output signals.
2. Description of the Prior Art
Generally, liquid crystal displays (LCDs) display images utilizing electric fields to control the light transmittance characteristics of liquid crystal material. Accordingly, LCDs include a liquid crystal display panel having liquid crystal cells arranged in a matrix pattern and a driving circuit for driving the liquid crystal display panel.
Gate lines and data lines are arranged within the liquid crystal display panel such that their arrangement caused them to cross each other. Liquid crystal cells are arranged at crossings of the gate and data lines. Liquid crystal display panels include pixel electrodes and a common electrode that apply electric fields to each of the liquid crystal cells. Each pixel electrode is connected to a corresponding data line via source or drain terminals of a switching device such as a thin film transistor (TFT). A gate terminal of each of the thin film transistors is connected to a corresponding gate line.
Driving circuits include a gate driver and a data driver. The gate driver sequentially drives the liquid crystal cells on the liquid crystal display panel by sequentially applying a scanning signal to the gate lines. When the gate lines are supplied with the scanning signal, the data driver applies a video signal to respective ones of the data lines. Pictures are displayed by applying an electric field between pixel electrodes of each of the liquid crystal cells in the LCD panel and the common electrode. Electric fields are applied in accordance with inputted video signals.
Dynamic shift registers are the most frequently utilized devices to generate the scanning signal. Please refer to FIG. 1. FIG. 1 shows a prior art shift register circuit 100. The shift register circuit 100 contains six dynamic shift registers 110 through 160, each of which has the same inner circuit shown in FIG. 2. The function of the circuit shown in FIG. 2 is well known to those skilled in the art, so the detailed description is omitted for brevity. Please refer to both FIG. 1 and FIG. 2. Each dynamic shift register has three input terminals, IN, C1, and C2, and an output terminal OUT. The dynamic shift register 110 receives an input signal (i.e., a start-up signal) STV at the input terminal IN. Other dynamic shift registers 120 through 160 receive the output signal of the preceding dynamic shift register as its own input signal. For example, the dynamic shift register 120 receives the output signal outputted at the output terminal OUT of the dynamic shift register 110 as its own input signal. The two input terminals C1 and C2 of each dynamic shift register 110 through 160 receive clock signals. Two adjacent dynamic shift registers alternatively receive two clock signals CK1 and CK2 respectively at these two input terminals C1 and C2. For example, the dynamic shift register 110 receives the clock signal CK1 at the input terminal C1, and receives the clock signal CK2 at the input terminal C2; however, the dynamic shift register 120 receives the clock signal CK2 at the input terminal C1, and receives the clock signal CK1 at the input terminal C2. The waveforms of the input signal STV, the two clock signals CK1 and CK2, and the output signals G1 through G6 are shown in FIG. 3.
As shown in FIG. 3, the output signals of two adjacent dynamic shift registers, e.g. G1 and G2, are overlapped. In some applications, output signals that are not overlapped are required. Therefore, if the aforementioned shift register circuit 100 is implemented in a vertical shift register circuit, an additional circuit is needed by the vertical shift register circuit to generate non-overlapped output signals according to these overlapped output signals generated from the shift register circuit 100. Please refer to FIG. 4. A logic circuit 400 is utilized to split overlapped output signals. The logic circuit 400 comprises a NAND gate 410 and an inverter 420. The NAND gate 410 receives three input signals that consist of two output signals of two adjacent dynamic shift registers, e.g. G1 and G2, and a signal ENB. It is apparent that the output signal X1 of the logic circuit 400 is equal to “G1•G2•ENB”. FIG. 5 shows the waveforms of three output signals of the shift register circuit 100, e.g. G1, G2, and G3, the signal ENB, and two split signals X1 and X2. Two logic circuits are required to split the output signals G1, G2, and G3. The first logic circuit receives signals G1, G2, and ENB, and therefore within the interval from t2 to t3 when all these three signals G1, G2, and ENB are at a high level, the first logic circuit generates the output signal X1 of a high logic level. Similarly, the second logic circuit receives signals G2, G3, and ENB, and therefore within the interval from t3 to t4 when all these three signals G2, G3, and ENB are at a high level, the second logic circuit generates the output signal X2 of a high logic level. As a result, non-overlapped output signals X1 and X2 are generated. Consequently, more non-overlapped output signals can be generated by utilizing the logic circuit 400.
However, each logic circuit requires a level shifter to shift the voltage level of the signal ENB from 3V to 8.5V. As more logic circuits are utilized, more level shifters are required. Unfortunately, additional level shifters result in increased power consumption.